In integrated circuit (IC) designs, nodes need to have logic constants at times. Nearly all digital circuits use a consistent logic level for all internal signals. That level, however, varies from one system to another. Interconnecting any two logic families often required special techniques such as additional pull-up resistors or purpose-built interface circuits known as level shifters. A level shifter connects one digital circuit that uses one logic level to another digital circuit that uses another logic level.
Isolation cells are used to prevent short circuit current. As the name suggests, these cells isolate a power gated block from the normally-on block. Isolation cells are specially designed for low short circuit current when input is at threshold voltage level. Isolation control signals are provided by the power gating controller. Isolation of the signals of a switchable module is essential to preserve design integrity. Usually a simple OR or AND logic can function as an output isolation device.
Instead of directly connecting a node requiring constant logic to VDD or VSS, which can have reliability implications (e.g., gate oxide damage), tie cells are used. Tie cells are components that can implement logic constants, i.e. ‘1’ (or VDD) and ‘0’ (or VSS). As shown in FIG. 1, there are two tie cells 110, 120 in a standard cell area. A tie cell 110 shown at left in FIG. 1 is a tie high cell (output at Y 130 is VDD 140) and the right tie cell 120 is a tie low cell (output at Y 150 is VSS 160). As a standard cell, a tie cell can reuse PG stripes (power and ground stripes) to save on routing resources.
However, new violations are introduced when only these tie cells are used to implement constant logic, and the design requires extra cells to fix the violations. As an example of such violations, in FIG. 2, the related supply of the load pin 220 of a macro 210 is supply VDD108AO 230. Supply VDD108AO 230, in this example, has the same voltage as primary supply VDD108SD 240, but macro 210 has a different power on/off state requirement as compared to the primary supply 240. If a tie cell 250 according to the design shown in FIG. 1 is used for constant logic implementation, an additional isolation cell (ISO) 260 is needed in to resolve the voltage or power state difference between the tie cell 250 and the load pin 220 of the macro 210.
It will be appreciated that, as used herein, the term macro refers to a macrocell array, which is an approach to the design and manufacture of ASICs. A macrocell array is a small step up from the otherwise similar gate array, but rather than being a prefabricated array of simple logic gates, the macrocell array is a prefabricated array of higher-level logic functions such as flip-flops, ALU functions, registers, and the like.
As another example, in FIG. 3, the voltage of the load supply voltage VDD108AO 330 is different than that of the primary supply VDD90AO 340. If a tie cell 350 according to the design shown in FIG. 1 is used for constant logic implementation, an additional level shifter cell (LS) 360 is needed to adjust for the voltage or power state difference between the tie cell 350 and the load pin 320 of the macro 310.